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2026 顶会论文

作者位次 #7/8ISCA 2026Oral· Computer Architecture

AutoFHE: An Automatic Hardware Generation Framework for Domain-Specific FHE Accelerators

Yibo Du · Cangyuan Li · Bing Li · Mengdi Wang · Lian Liu · Shixin Zhao · Yinhe Han · Ying Wang

长上下文与架构OpenReview

作者位次 #3/4ISCA 2026Oral· Computer Architecture

ConBin: a Performance-Convergence Framework for Wafer-Scale Chip Binning

Huiqing Xu · Mengdi Wang · Yinhe Han · Ying Wang

长上下文与架构OpenReview

作者位次 #4/5ISCA 2026Oral· Computer Architecture

Unlocking Pipeline Parallelism for Bootstrapping: A Pipelined Multi-Chiplet TFHE Accelerator

Yibo Du · Mengdi Wang · Cangyuan Li · Yinhe Han · Ying Wang

长上下文与架构OpenReview

作者位次 #4/6MICRO 2026Oral· Accelerator Spatial Mapping & High-Level Synthesis

UDYR: An Adaptive Accelerator for Optimization-based Humanoid Robot Control

Yuhui Hao · Bo Yu · Shaoshan Liu · Yinhe Han · Yu Feng · Yiming Gan

社会与人本OpenReview

作者位次 #8/12MICRO 2026Oral· Vision-Language & Multimodal Model Acceleration

Deltoris: Enabling Real-time VLA Inference in Embodied AI via Bit-level Sparsity and Speculative Inference

Zheng Liu · Zeyu Guo · Zihan Liu · Anbang Wu · Han Zhao · Fangxin Liu · Zhezhi He · Yinhe Han · Jingwen Leng · Minyi Guo · Yiming Gan · Yu Feng

效率与系统多模态OpenReview

作者位次 #5/6MICRO 2026Oral· PIM & Near-Memory Long-Context LLM Serving

Rethinking Unified Memory for NPU–PIM Systems: Dual-View Memory for Dynamic Inference of LLM

Shixin Zhao · Lian Liu · Tianhua Han · Mengdi Wang · Yinhe Han · Ying Wang

效率与系统检索与知识长上下文与架构OpenReview

作者位次 #10/11MICRO 2026Oral· Systolic & Dataflow Innovations for LLM/GNN Inference

One Chiplet to Build Them All: Cost-Efficient Hardware Specialization for Stage-Separated LLM Inference

Haonan Zhu · Mengdi Wang · Haoyi Jiang · Danqing Zhang · Lian Liu · Shixin Zhao · Yutian Zhou · Yudong Pan · Tianhua Han · Yinhe Han · Ying Wang

效率与系统OpenReview

作者位次 #9/11ACL 2026Poster· Natural Language Processing

C hip S eek: Optimizing Verilog Generation via EDA -Integrated Reinforcement Learning

Zhirong Chen · Kaiyan Chang · Zhuolin Li · Cangyuan Li · Xinyang He · Chujie Chen · Mengdi Wang · Haobo Xu · Yinhe Han · Huawei Li · Ying Wang

摘要

Large Language Models have emerged as powerful tools for automating Register-Transfer Level (RTL) code generation, yet they face critical limitations: existing approaches typically fail to simultaneously optimize functional correctness and hardware efficiency metrics such as Power, Performance, a...

强化学习与后训练评测与基准可解释性OpenReview 项目页

Yinhe Han

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2026 顶会论文

AutoFHE: An Automatic Hardware Generation Framework for Domain-Specific FHE Accelerators

ConBin: a Performance-Convergence Framework for Wafer-Scale Chip Binning

Unlocking Pipeline Parallelism for Bootstrapping: A Pipelined Multi-Chiplet TFHE Accelerator

UDYR: An Adaptive Accelerator for Optimization-based Humanoid Robot Control

Deltoris: Enabling Real-time VLA Inference in Embodied AI via Bit-level Sparsity and Speculative Inference

Rethinking Unified Memory for NPU–PIM Systems: Dual-View Memory for Dynamic Inference of LLM

One Chiplet to Build Them All: Cost-Efficient Hardware Specialization for Stage-Separated LLM Inference

C hip S eek: Optimizing Verilog Generation via EDA -Integrated Reinforcement Learning

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