V erilog LAVD : LLM -Aided Pattern Generation for Verilog CWE Detection
Xiang Long · Yingjie Xia · Li Kuang · Yao Wan · ZiHao Liu
摘要
LLMs often fail in hardware vulnerability detection due to the intrinsic semantic concurrency of HDLs (Hardware Description Language), where vulnerabilities arise from the interaction of multiple concurrent execution statements rather than a single sequential execution path. To address the proble...